I am using a CPLD to generate the SPI-type interface, running the clock at about 32kHz.
Reset state is strobe high, clock high.
Strobe asserted low 1/2 clock period, then clock is set low.
16 cycles on clock, then strobe deasserted high 1/2 clock period later.
Data is driven on falling edges of clock, held stable on rising edges. Sending MSB first.
strobe is deasserted one clock period between write cycles, clock held high during idle period.
I am waiting approx. 250 microseconds between power application and transmission of Function Set command.