Author Topic: Lower Limit for SPI-Clock Cycle?  (Read 3928 times)


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Lower Limit for SPI-Clock Cycle?
« on: March 27, 2015, 06:01:48 AM »
I'm working with a NHD-0216CW display in SPI mode and had some problems to bring it up and running in the last days. Finally, the problem was a mistake in the datasheet in the power-supply section, but before I found this issue, I tended to believe I made something wrong in the SPI-protocol. In cases like this, it's very helpful to have the possibility to go stepwise through the programcode and observe signals statically. In the datasheet I see a lower limit for the clock period of (20us) when using the SPI-interface mode. Is this a typo or is it a fact that the design of the SPI-interface is NOT statically? After everything worked, i dramatically slowered down the bus speed just to see if it still works and it did. (Of Course, it makes no sense to use the display with such a bus speed except for debugging. E.g. in the I2C- definition, there is no given lower limit for the Clock cycle)   


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Re: Lower Limit for SPI-Clock Cycle?
« Reply #1 on: March 29, 2015, 04:42:01 PM »
The 20us max clock period rating is correct to achieve reliable operation.  This is a specification of the controller IC the display uses.


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