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Messages - mike_s

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1
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« on: July 05, 2019, 03:29:32 PM »
Finally,

7.0" TFT is working perfect, thanks so much, I have both 5.0" and 7.0" working awesome!

BTW, also verified that the 'Data Enable' is indeed 'ACTIVE HIGH', so STMicro has an error in their datasheet..

here's the scope shot, showing DE active high and a bit of the RBG data lines...

(DE ==> Yellow)
(RBG bit ==> Green)


2
Hi,

I looked over the Arduino and FT81x schematics, the FT81x shield gets ALL of it's power from the arduino power header, so you absolutely MUST use a good DC power supply for that arduino DC jack.  (USB definitely does not have the current capability to power everything)

you ONLY need that one single source for your power, that DC jack on the arduino, but you must use a good supply, go for 1000mA or better....

sounds to me from your heat problems and voltage readings your power supply is too weak, and in the other experiments you were shorting two power supplies together...


1) You may want to try and 'isolate' your problems if possible, as you may have damaged your screens initially when you were breadboarding them, before you got the FT81x shield..

   a) disconnect the TFT from the FT81x shield, and just power up the Arduino + FT81x board together, make sure they stay on and you feel ZERO
       heat anywhere...

   b) measure voltages on those connectors (ie still without TFT) and verify voltages are 3.3 and 5.0, ie they should NOT be lower..


*** ALL of this to be done with  GOOD DC POWER SUPPLY (1000mA or better) into that Arduino DC jack ONLY ***
(do not apply power directly to anywhere else)

3
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« on: June 19, 2019, 06:46:34 PM »
Hi Mike_S,

It's good to hear you have it working!

You are correct that the 7.0" TFT is setup to work in DE mode by default.  The display's Data Enable mode is Active High at pin 34 to enable the data input bus.

Best Regards,

Hi Ted,


If you all are certain that the pin34 DE is definitely ACTIVE HIGH logic, then that means STMicro messed up their data sheet, since I had to set the LTDC -> DE polarity to 'Active Lo'....

but of course their wording could also be a 'double negative', when they say 'not data enable polarity is active low'... which would mean Active Hi. LOL

anyhow, this is good info for anyone that ends up using an STM32xxx processor with the LTDC controller, so they know the datasheet is backwards...

4
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« on: June 19, 2019, 03:27:58 PM »
Ok,

I got it all working... the DE POLARITY was backwards, at least according to the STM32H7 datasheet, so I don't know whom is right, the NewHaven TFT datasheet, or the STM32H7 datasheet.

But in order for DE to work, I had to set:

** From the STM32H7 datasheet **


Code: [Select]
DEPOL: not data enable polarity
This bit is set and cleared by software.
0: not data enable polarity is active low.   <<<==== had to set to ACTIVE LOW
1: not data enable polarity is active high.

with it ACTIVE HIGH there is NO display.... only thing I could do to prove it out would be to scope it up, but right now I just want to install the screen and get it working.

(I also verified I could disable DE altogether by installing that R4 short, which I did to verify the screen worked, then removed it, as I want to use the default of 'DE' being enabled.


So for now the screen works!  But I'm concerned as to which vendor is right... is the STMicro datasheet backwards, or is the datasheet wrong for the LCD, and 'DE' is actually ACTIVE LOW, not high?


5
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« on: June 19, 2019, 10:42:17 AM »
Actually,

I think I see something, I'll be trying this today when I get home from work...

1) PCLK needs to be inverted for this LCD

2) ** most ** important, sounds like this 7.0" TFT is setup by default to use 'DE' mode, whereas the 5.0" probably was not?

(my LTDC controller does have the DE pin, but by default it was setup as 'active LOW', and I have the pin pulled down), so it sounds like the 5.0" was probably not using it which is why my setup still worked, but the 7.0" I need to switch the pin polarity)


Ie I see a discussion just like this in a old thread from 2014..

https://www.newhavendisplay.com/NHD_forum/index.php/topic,67.15.html


I'll report back after testing this evening :)




6
TFTs / NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« on: June 19, 2019, 05:54:59 AM »
Hi All,

I have a current project using an STM32H7 micro, which has a built-in LTDC display controller.  I have it working fine with the 5.0" display as mentioned in the topic.

I wanted to then see how much better it would be with the 7.0" display, which appears to be an identical electrical interface, with the exception of the LCD Backlight voltage being 9.6V on the 7.0" versus 19.2V on the 5.0".

I realize the controller chips changed:

1) 5.0" ==  ILI6126C
2) 7.0" == HX8264-D02


I tried the 7.0" display on both of my boards (which both work fine with 5.0" displays), and I get absolutely nothing on the screens except for the initial white backlight when it first boots up...

I've played with the timings, I/O drive strength, pixel clock, etc, with zero effect. 

I did notice that the PCLK on the 5.0" says it's rising edge triggered, versus the 7.0" which is falling edge triggered.. but I haven't tried inverting the PCLK polarity yet, do I need to make that change for the 7.0" TFT?

Is anyone aware of anything else that may need to be changed when going from the ILI6126C controller to the HX8264??


(I've opened an RMA request suspecting that the display may be bad, but I realize they do test these screens before they are shipped out, so I wonder if there is still something I'm missing???)


Thanks so much,

- Mike

7
TFTs / Re: Image Alignment - 480x272 image on 800x480 TFT
« on: May 22, 2019, 09:25:31 AM »
I was able to add 22R resistors to the CLK, HSYNC, VSYNC and DEN and reduced the drive current on the RGB lines and now I seem to have a more stable display although I do see some horizontal shift when I use anything but black on the left side of the LCD, but it is looking closer now to being a working LCD.

Hi Dave,

that's good, I was going to suggest (if by chance you are using an STM32 or similar where you can change the I/O drive strength), to set the I/O 'strength', or in STM32 case, the 'speed', as this made a BIG difference in the I/O signals and reflections...

I think I have mine set at 'HIGH', which seemed the best (ie VERY HIGH is more in the ballpark of 100mhz or more like SDRAM, etc)

Also, play with your pixel clock and see if slowing it down a bit cleans up your picture too... as I was saying, I am good at 24Mhz, if I go to 30Mhz or higher, I get distortion, even with all the I/O cleanup I have, it's still not good.. so for now 24mhz is fine for my setup..


but I could probably figure it out if I scope'd it up again and did more resistance tweaking, but for now I'm ok with where it's at, I have 68R series resistors on my lines, I did all lines with my last board spin..

- Mike

8
TFTs / Re: Image Alignment - 480x272 image on 800x480 TFT
« on: May 20, 2019, 09:25:57 AM »
The offset shown in that image was because the datasheet in 2018 for this TFT had the  HBP (Horizontal Back Porch) value as 88 pixel clocks, which through trial and error testing I found out was waaayyy too high.  I turned out the HBP needed to be in the 40s area.

This is interesting to know. I have a 7.0" with 800x480 and in the timing, it has HBP also as 88 clocks. I got some timing from Newhaven tech that sets the HBP to 40. I have tried this and the display is much better but I still get tearing and some artifacts on the display. Can I ask what other timing values you used for your 5.0" display? I think the 5 and 7 are the same except for the clock which is latched on the positive edges on the 5.0"

Cheers
Dave...

Hi Dave,

I don't have my code in front of me at the moment, but I remember checking the other day against the latest datasheet, and my timing numbers now match exactly what is in the sheet, so I didn't have to tweak anything else...

Although, I DO encounter similar problems if I push the pixel clock closer to their recommended values of 30-50Mhz...  now it could very well be my board layout, since I didn't do any meandering for the bus lines...I do have series termination, as I originally saw a good bit of reflection on the scope... they are much cleaner now..

So, I am currently running my pixel clock at 24Mhz, which is 100% clean with no tearing or artifacts... if I push it to 30Mhz and up, things start to go bad...


9
TFTs / Re: Image Alignment - 480x272 image on 800x480 TFT
« on: May 17, 2019, 08:09:19 AM »
Hi All,

Just wanted to update, that this issue can now be CLOSED as SOLVED.

The offset shown in that image was because the datasheet in 2018 for this TFT had the  HBP (Horizontal Back Porch) value as 88 pixel clocks, which through trial and error testing I found out was waaayyy too high.  I turned out the HBP needed to be in the 40s area.

Looks like the datasheet has been updated recently, and it's showing correct values now for HBP as well as better timings for the other values.


So this TFT is indeed working awesome now, no issues whatsoever!

Thanks so much,


- Mike

10
TFTs / Image Alignment - 480x272 image on 800x480 TFT
« on: January 12, 2019, 06:09:24 PM »
Hi Everyone,

I'm just getting through some initial debugging on my board using an STM32H7, connected to the :  NHD-5.0-800480TF-ATXL-CTP
(800x480 TFT)

I'm using the STM32H7 built-in LTDC display controller... STM has sample code/etc for testing out the LCD screen, etc..

so their eval setup used a 480x272 LCD display, whereas I'm using this one above, 800x480..

so after setting up the params correctly, I can display their test image, but I would have expected for the image to have started at the left-side origin, but there is some blank space...

What I'm wondering is if this could happen from an I/O being wrong or shorted?  or would I see scrambled data if that was the case?

11
TFTs / Active Lo/Active Hi signals for these TFTs?
« on: January 06, 2019, 12:36:45 PM »
Hi Everyone,

I'm currently working on my initial setup with this TFT: NHD-5.0-800480TF-ATXL-CTP

The datasheets don't specifically call out or mark the signals as Active Hi or Active Lo... these are the signals for this panel:

 
Pin No.    Symbol    External Connection    Function Description       
1    LED-    LED Power Supply    Ground for Backlight    
 
2    LED+    LED Power Supply    Backlight Power Supply (60mA @ ~19.2V)       
3    GND    Power Supply    Ground       
4    VDD    Power Supply    Power supply for LCD and logic (3.3V)       
5-12    [R0-R7]    MPU    Red Data Signals       
13-20    [G0-G7]    MPU    Green Data Signals       
21-28    [B0-B7]    MPU    Blue Data Signals       
29    GND    Power Supply    Ground       
30    CLKIN    MPU    Clock for input data (Rising Edge)       
31    STBYB    MPU    1: Normal Operation;0: Standby Mode       
32    HSD    MPU    Line synchronization signal      ****   PULL-UP?  ****
33    VSD    MPU    Frame synchronization signal      ****  PULL-UP? ****
34    DEN    MPU    Data Enable signal       
35    NC    -    No Connect       
36    GND    Power Supply    Ground       
37    XR    -    No Connect       
38    YD    -    No Connect       
39    XL    -    No Connect       
40    YU    -    No Connect    


 
Pin No.    Symbol    External Connection    Function Description       
1    VCC    Power Supply    Power supply for logic (3.0V)       
2    GND    Power Supply    Ground       
3    SCL    MPU    Serial I2C Clock (Requires pull-up resistor)       
4    SDA    MPU    Serial I2C Data (Requires pull-up resistor)       
5    /INT    MPU    Interrupt signal from touch panel module to host        ****   PULL-UP  ****
6    /RESET    MPU    Active LOW Reset signal                                        ****   PULL-UP  ****



From the timing diagrams, It seems that ONLY  VSD, HSD, INT, & RESET are active LO signals?  all the rest are Active HI, ie default state is pulled down..

Can anyone verify that this is correct, ONLY VSD, HSD, INT, & RESET need to be pulled-up?

Thanks so much,

- Mike



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