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Topics - bivin

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TFTs / EVE2 TFT Modules VHDL Coding
« on: October 03, 2018, 04:39:53 AM »
Hi
I'm using NHD-3.5-320240FT-CSXN-CTP. As per FT81x Series Programmers Guide, in " Initialization Sequence during the boot up" section , display list writing is given by below functions.

wr32(RAM_DL+0,CLEAR_COLOR_RGB(0,0,0));
wr32(RAM_DL+4,CLEAR(1,1,1));
wr32(RAM_DL+8,DISPLAY());
wr8(REG_DLSWAP,DLSWAP_FRAME);//display list swap
wr8(REG_GPIO_DIR,0x80|rd8(REG_GPIO_DIR));
wr8(REG_GPIO,0x080|rd8(REG_GPIO));//enable display bit
wr8(REG_PCLK,5);//after this display is visible on the LCD
MCU_SPI_CLK_Freq(<30Mhz);//use the MCU SPI clock upto 30MHz

Kindly let me know what are the equivalent register read/write (w.r.t DS_FT81x.pdf) to implement the above in vhdl.

Thanks


2
TFTs / EVE2 TFT Module VHDL Code Support (NHD-3.5-320240FT-CSXN-CTP)
« on: March 19, 2018, 12:06:34 AM »
I'm using NHD-3.5-320240FT-CSXN-CTP. But the device manual is not clear on how to program the module through SPI/QSPI interface using FPGA. Kindly explain how to initialize the module from FPGA. Sent "CLKEXT" , "ACTIVE" etc are bit unclear. Kindly share additional documents for the same. :-[

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