Author Topic: NHD-3.12-25664UCB2 Contrast Inconsistencies  (Read 948 times)


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NHD-3.12-25664UCB2 Contrast Inconsistencies
« on: January 15, 2019, 11:04:54 AM »
Hello. Below are two pictures showing what my display looks like when I run the 0xA5 command, turning all pixels to max brightness GS15, under two different contrast levels. The first contrast level - 0x7F, produces a consistent brightness, but the second contrast level- 0xFF displays regular brightness variations in the horizontal direction. I will also provide my intialization sequence as well. I haven't tried all contrast levels yet, but every contrast level other than 0x7F i have tried seems to also give an irregular display pattern for maximum brightness.

0x7F contrast:

0xFF contrast:

Code: [Select]
oled_send_cmd(oled, SET_CMD_LOCK);
oled_send_data(oled, 0x12); // 0x12 allows the dislplay MCU to receive commands. 0x16 locks MCU

oled_send_cmd(oled, SET_FRONT_CLK_DIV);
oled_send_data(oled, 0x91); // first 4 bits is the clock divider, 0xD0 sets divider to 1. second 4 bits specified frequency of the clock.

oled_send_cmd(oled, SET_MULTIPLEX_RATIO);
oled_send_data(oled, 0x3F); // Sets the number of common pins, each of which control one row. 0x3F corresponds to 64 rows.

oled_send_cmd(oled, SET_DISP_OFFSET);
oled_send_data(oled, 0x0); // Specifies which row the display will start with.
      // 0x0 = starting at row 0. Non zero value will cause vertical wrapping

oled_send_cmd(oled, SET_DISP_START_LN);
oled_send_data(oled, 0x0); // Functionally the same as SET_DISP_OFFSET

oled_send_cmd(oled, SET_REMAP_DUAL_COM);
oled_send_data(oled, 0x06);  // first bit Sets Horizontal Address Increment (writing to display ram will wrap to next row)
         // second bit Sets Column Address Remap - Pixels are represented by nibbles called segments. There are 4 segments in a column.
// This maps Columns 0 - 119 -> SEG(476-479 ~ 0-3 ), backwards.
        // third bit Enables Nibble Re-map. Each nibble in a column maps to pixels in horizontal reading order.
        // fourth bit Rows are displayed first to last
       // fifth bit disables COM Split Odd Even: Com 0 will correspond to Row 0
oled_send_data(oled, 0x0);  // fifth bit disables dual com mode (row's contents are split betwee two coms.)

oled_send_cmd(oled, SET_GPIO); // Disables gpio input pins
oled_send_data(oled, 0x00);

oled_send_cmd(oled, SET_FUNC_SEL);
oled_send_data(oled, 0x01); // Uses internal voltage regulattor

oled_send_cmd(oled, ENHANCE_A);
oled_send_data(oled, 0xA0); // first bit 0 enables external Voltage low reference signal
oled_send_data(oled, 0xB5); // Normal display quality

oled_send_cmd(oled, SET_CONTRAST_CURRENT);
oled_send_data(oled, 0xFF); // Sets contrast leevl of display, higher value gives higher contrast (max 256)

oled_send_cmd(oled, MASTER_CURR_CTRL);
oled_send_data(oled, 0x0F); // first 4 bits - sets output current. Lower values reduce output current.

oled_send_cmd(oled, SET_DEF_LN_GRAYSCALE_TBL); // Uses default gray scale table for brightness of pixels.

oled_send_cmd(oled, SET_PHASE_LENGTH); // first 4 bits, sets phase 1 period to 5 clocks. Second 4 bits sets phase 2 period, set to 7 clocks
oled_send_data(oled, 0xE2);

oled_send_cmd(oled, ENHANCE_B);
oled_send_data(oled, 0x82); // Set to "enhance display performance".
oled_send_data(oled, 0x20); // Required to send, is not configurable

oled_send_cmd(oled, SET_PRE_CHARGE_VOLTAGE);
oled_send_data(oled, 0x1F); // sets precharge voltage to 0.6 * Vcc

oled_send_cmd(oled, SET_SECOND_PRE_CHARGE_PERIOD);
oled_send_data(oled, 0x08); // prechage period is 8 clocks

oled_send_cmd(oled, SET_VCOMH);
oled_send_data(oled, 0x07);  // sets vcomh to 0.86 * Vcc

oled_send_cmd(oled, SET_DISPLAY_WHITE);  // Normal, as opposed to off or inverted

oled_send_cmd(oled, EXIT_PARTIAL_DISP);

oled_send_cmd(oled, SET_SLEEP_MODE_OFF);


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