Author Topic: Color problem with NHD-5.0-800480TF-ATXL-CTP  (Read 2971 times)

mozart

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Color problem with NHD-5.0-800480TF-ATXL-CTP
« on: September 30, 2014, 07:30:33 AM »
Dear Sirs,

I think it is a simple problem but I'm a newbie in automation, so, I need help.

I'm using Olimex LPC-2478 board (NXP ARM7).

Right now, I make efforts in order to change the display of ours equipments from the
NHD-5.7-6-640480WF-CTX with SSD1963_1.1 (touchscreen) to Newhaven NHD-5.0-800480TF-ATXL-CTP.

Although I have no experience with the new display, I have tryed the below code based
on the one for the previous display.

Almost everything works fine (including the touch screen not showed here).

Only one situation remains without solution: I don't get the right colors at the display. I get the basic colors red, green and blue separately
(0xFF0000, 0x00FF00 and 0x0000FF), but when these color are mixed, for example to make yellow,
the resultant colour is not achieved.

In order to decrease the time you need in helping me, I made a simple code to write a pixel at
the full window using c language. Inside that code I put all the basic definitions.

May you see the code below and help me?

Advance thanks,


//
// Code Snippet
//

#define PX_BG                   0x857047

#define C_GLCD_H_SIZE_MM        109
#define C_GLCD_V_SIZE_MM        66
#define C_GLCD_REFRESH_FREQ     (50HZ)
#define C_GLCD_H_SIZE           800
#define C_GLCD_H_PULSE          5

// Basic definitions
#define C_GLCD_H_FRONT_PORCH    40
#define C_GLCD_H_BACK_PORCH     88
#define C_GLCD_V_SIZE           480
#define C_GLCD_V_PULSE          3
#define C_GLCD_V_FRONT_PORCH    13
#define C_GLCD_V_BACK_PORCH     32
#define C_GLCD_SIZE             C_GLCD_H_SIZE * C_GLCD_V_SIZE
#define C_GLCD_PWR_ENA_DIS_DLY  10000
#define C_GLCD_ENA_DIS_DLY      10000
#define LCD_VRAM_BASE_ADDR ((Int32U)&SDRAM_BASE_ADDR)
#define LCD_CURSOR_BASE_ADDR ((Int32U)0xFFE10800)

// Registers
__IO_REG32_BIT(LCD_CFG,               0xE01FC1B8,__READ_WRITE ,__lcd_cfg_bits);
__IO_REG32_BIT(LCD_TIMH,              0xFFE10000,__READ_WRITE ,__lcd_timh_bits);
__IO_REG32_BIT(LCD_TIMV,              0xFFE10004,__READ_WRITE ,__lcd_timv_bits);
__IO_REG32_BIT(LCD_POL,               0xFFE10008,__READ_WRITE ,__lcd_pol_bits);
__IO_REG32_BIT(LCD_LE,                0xFFE1000C,__READ_WRITE ,__lcd_le_bits);
__IO_REG32(    LCD_UPBASE,            0xFFE10010,__READ_WRITE );
__IO_REG32(    LCD_LPBASE,            0xFFE10014,__READ_WRITE );
__IO_REG32_BIT(LCD_CTRL,              0xFFE10018,__READ_WRITE ,__lcd_ctrl_bits);
__IO_REG32_BIT(LCD_INTMSK,            0xFFE1001C,__READ_WRITE ,__lcd_intmsk_bits);
__IO_REG32_BIT(LCD_INTRAW,            0xFFE10020,__READ       ,__lcd_intraw_bits);
__IO_REG32_BIT(LCD_INTSTAT,           0xFFE10024,__READ       ,__lcd_intstat_bits);
__IO_REG32_BIT(LCD_INTCLR,            0xFFE10028,__WRITE      ,__lcd_intclr_bits);
__IO_REG32(    LCD_UPCURR,            0xFFE1002C,__READ       );
__IO_REG32(    LCD_LPCURR,            0xFFE10030,__READ       );
__IO_REG32(    LCD_PAL_BASE,          0xFFE10200,__READ_WRITE );
__IO_REG32(    CRSR_IMG_BASE,         0xFFE10800,__READ_WRITE );
__IO_REG32_BIT(CRSR_CTRL,             0xFFE10C00,__READ_WRITE ,__crsr_ctrl_bits);
__IO_REG32_BIT(CRSR_CFG,              0xFFE10C04,__READ_WRITE ,__crsr_cfg_bits);
__IO_REG32_BIT(CRSR_PAL0,             0xFFE10C08,__READ_WRITE ,__crsr_pal0_bits);
__IO_REG32_BIT(CRSR_PAL1,             0xFFE10C0C,__READ_WRITE ,__crsr_pal1_bits);
__IO_REG32_BIT(CRSR_XY,               0xFFE10C10,__READ_WRITE ,__crsr_xy_bits);
__IO_REG32_BIT(CRSR_CLIP,             0xFFE10C14,__READ_WRITE ,__crsr_clip_bits);
__IO_REG32_BIT(CRSR_INTMSK,           0xFFE10C20,__READ_WRITE ,__crsr_intmsk_bits);
__IO_REG32_BIT(CRSR_INTCLR,           0xFFE10C24,__WRITE      ,__crsr_intclr_bits);
__IO_REG32_BIT(CRSR_INTRAW,           0xFFE10C28,__READ       ,__crsr_intraw_bits);
__IO_REG32_BIT(CRSR_INTSTAT,          0xFFE10C2C,__READ       ,_

/* LCD Configuration register */
typedef struct{
__REG32 CLKDIV          : 5;
__REG32                 :27;
}__lcd_cfg_bits;


/* Horizontal Timing register */
typedef struct{
__REG32                 : 2;
__REG32 PPL             : 6;
__REG32 HSW             : 8;
__REG32 HFP             : 8;
__REG32 HBP             : 8;
}__lcd_timh_bits;

/* Vertical Timing register */
typedef struct{
__REG32 LPP             :10;
__REG32 VSW             : 6;
__REG32 VFP             : 8;
__REG32 VBP             : 8;
}__lcd_timv_bits;

/* Clock and Signal Polarity register */
typedef struct{
__REG32 PCD_LO          : 5;
__REG32 CLKSEL          : 1;
__REG32 ACB             : 5;
__REG32 IVS             : 1;
__REG32 IHS             : 1;
__REG32 IPC             : 1;
__REG32 IOE             : 1;
__REG32                 : 1;
__REG32 CPL             :10;
__REG32 BCD             : 1;
__REG32 PCD_HI          : 5;
}__lcd_pol_bits;

/* Line End Control register */
typedef struct{
__REG32 LED             : 7;
__REG32                 : 9;
__REG32 LEE             : 1;
__REG32                 :15;
}__lcd_le_bits;

/* LCD Control register */
typedef struct{
__REG32 LcdEn           : 1;
__REG32 LcdBpp          : 3;
__REG32 LcdBW           : 1;
__REG32 LcdTFT          : 1;
__REG32 LcdMono8        : 1;
__REG32 LcdDual         : 1;
__REG32 BGR             : 1;
__REG32 BEBO            : 1;
__REG32 BEPO            : 1;
__REG32 LcdPwr          : 1;
__REG32 LcdVComp        : 2;
__REG32                 : 2;
__REG32 WATERMARK       : 1;
__REG32                 :15;
}__lcd_ctrl_bits;

/* Interrupt Mask register */
typedef struct{
__REG32                 : 1;
__REG32 FUFIM           : 1;
__REG32 LNBUIM          : 1;
__REG32 VCompIM         : 1;
__REG32 BERIM           : 1;
__REG32                 :27;
}__lcd_intmsk_bits;

/* Raw Interrupt Status register */
typedef struct{
__REG32                 : 1;
__REG32 FUFRIS          : 1;
__REG32 LNBURIS         : 1;
__REG32 VCompRIS        : 1;
__REG32 BERRAW          : 1;
__REG32                 :27;
}__lcd_intraw_bits;

/* Masked Interrupt Status register */
typedef struct{
__REG32                 : 1;
__REG32 FUFMIS          : 1;
__REG32 LNBUMIS         : 1;
__REG32 VCompMIS        : 1;
__REG32 BERMIS          : 1;
__REG32                 :27;
}__lcd_intstat_bits;

/* Interrupt Clear register */
typedef struct{
__REG32                 : 1;
__REG32 FUFIC           : 1;
__REG32 LNBUIC          : 1;
__REG32 VCompIC         : 1;
__REG32 BERIC           : 1;
__REG32                 :27;
}__lcd_intclr_bits;

/* Cursor Control register */
typedef struct{
__REG32 CrsrOn          : 1;
__REG32                 : 3;
__REG32 CrsrNum         : 2;
__REG32                 :26;
}__crsr_ctrl_bits;

/* Cursor Configuration register */
typedef struct{
__REG32 CrsrSize        : 1;
__REG32 FrameSync       : 1;
__REG32                 :30;
}__crsr_cfg_bits;

/* Cursor Palette register 0 */
typedef struct{
__REG32 Red             : 8;
__REG32 Green           : 8;
__REG32 Blue            : 8;
__REG32                 : 8;
}__crsr_pal0_bits;

/* Cursor Palette register 1 */
typedef struct{
__REG32 Red             : 8;
__REG32 Green           : 8;
__REG32 Blue            : 8;
__REG32                 : 8;
}__crsr_pal1_bits;

/* Cursor XY Position register */
typedef struct{
__REG32 CrsrX           :10;
__REG32                 : 6;
__REG32 CrsrY           :10;
__REG32                 : 6;
}__crsr_xy_bits;

/* Cursor Clip Position register */
typedef struct{
__REG32 CrsrClipX       : 6;
__REG32                 : 2;
__REG32 CrsrClipY       : 6;
__REG32                 :18;
}__crsr_clip_bits;

/* Cursor Interrupt Mask register */
typedef struct{
__REG32 CrsrIM          : 1;
__REG32                 :31;
}__crsr_intmsk_bits;

/* Cursor Interrupt Clear register */
typedef struct{
__REG32 CrsrIC          : 1;
__REG32                 :31;
}__crsr_intclr_bits;

/* Cursor Raw Interrupt Status register */
typedef struct{
__REG32 CrsrRIS         : 1;
__REG32                 :31;
}__crsr_intraw_bits;

/* Cursor Masked Interrupt Status register */
typedef struct{
__REG32 CrsrMIS         : 1;
__REG32                 :31;
}__crsr_intstat_bits;


//
//  Initialization function
//
void GLCD_Init (const Int32U *pPain, const Int32U * pPallete){
  pInt32U pDst = (pInt32U) LCD_VRAM_BASE_ADDR;
  // Assign pin
  PINSEL0 &= BIN32(11111111,11110000,00000000,11111111);
  PINSEL0 |= BIN32(00000000,00000101,01010101,00000000);
  PINMODE0&= BIN32(11111111,11111100,00000000,11111111);
  PINMODE0|= BIN32(00000000,00000010,10101010,00000000);
  PINSEL3 &= BIN32(11110000,00000000,00000000,11111111);
  PINSEL3 |= BIN32(00000101,01010101,01010101,00000000);
  PINMODE3&= BIN32(11110000,00000000,00000000,11111111);
  PINMODE3|= BIN32(00001010,10101010,10101010,00000000);
  PINSEL4 &= BIN32(11110000,00110000,00000000,00000000);
  PINSEL4 |= BIN32(00000101,01001111,11111111,11111111);
  PINMODE4&= BIN32(11110000,00110000,00000000,00000000);
  PINMODE4|= BIN32(00001010,10001010,10101010,10101010);
  PINSEL9 &= BIN32(11110000,11111111,11111111,11111111);
  PINSEL9 |= BIN32(00001010,00000000,00000000,00000000);
  PINMODE9&= BIN32(11110000,11111111,11111111,11111111);
  PINMODE9|= BIN32(00001010,00000000,00000000,00000000);
  PINSEL11&= BIN32(11111111,11111111,11111111,11110000);
  PINSEL11|= BIN32(00000000,00000000,00000000,00001111);
  // Init GLCD cotroller
  PCONP_bit.PCLCD = 1;      // enable LCD controller clock
  CRSR_CTRL_bit.CrsrOn = 0; // Disable cursor
  LCD_CTRL_bit.LcdEn = 0;   // disable GLCD controller
  LCD_CTRL_bit.LcdBpp= 5;   // 24 bpp
  LCD_CTRL_bit.LcdTFT= 1;   // TFT panel
  LCD_CTRL_bit.LcdDual=0;   // single panel
  LCD_CTRL_bit.BGR   = 1;   // 0 = notmal output, 1 = red and blue swapped
  LCD_CTRL_bit.BEBO  = 0;   // little endian byte order
  LCD_CTRL_bit.BEPO  = 0;   // little endian pix order
  LCD_CTRL_bit.LcdPwr= 0;   // disable power
  // init pixel clock
  LCD_CFG_bit.CLKDIV =  SYS_GetFsclk() / (Int32U)C_GLCD_PIX_CLK;
  LCD_POL_bit.BCD    = 1;   // bypass internal clk divider
  LCD_POL_bit.CLKSEL = 0;   // clock source for the LCD block is HCLK
  LCD_POL_bit.IVS    = 1;   // LCDFP pin is active LOW and inactive HIGH
  LCD_POL_bit.IHS    = 1;   // LCDLP pin is active LOW and inactive HIGH
  LCD_POL_bit.IPC    = 1;   // data is driven out into the LCD on the falling edge
  LCD_POL_bit.IOE    = 0;   // active high
  LCD_POL_bit.CPL    = C_GLCD_H_SIZE-1;
  // init Horizontal Timing
  LCD_TIMH_bit.HBP   =  C_GLCD_H_BACK_PORCH - 1;
  LCD_TIMH_bit.HFP   =  C_GLCD_H_FRONT_PORCH - 1;
  LCD_TIMH_bit.HSW   =  C_GLCD_H_PULSE - 1;
  LCD_TIMH_bit.PPL   = (C_GLCD_H_SIZE/16) - 1;
  // init Vertical Timing
  LCD_TIMV_bit.VBP   =  C_GLCD_V_BACK_PORCH;
  LCD_TIMV_bit.VFP   =  C_GLCD_V_FRONT_PORCH;
  LCD_TIMV_bit.VSW   =  C_GLCD_V_PULSE;
  LCD_TIMV_bit.LPP   =  C_GLCD_V_SIZE - 1;
  // Frame Base Address doubleword aligned
  LCD_UPBASE         =  LCD_VRAM_BASE_ADDR & ~7UL ;
  LCD_LPBASE         =  LCD_VRAM_BASE_ADDR & ~7UL ;
  // init colour pallet

  if(NULL != pPallete)
  {
    GLCD_SetPallet(pPallete);
  }

  for(volatile Int32U i = C_GLCD_ENA_DIS_DLY; i; i--);
}

//
// Enable / disable function
//
void GLCD_Ctrl (Boolean bEna)
{
  if (bEna)
  {
    LCD_CTRL_bit.LcdEn = 1;
    for(volatile Int32U i = C_GLCD_PWR_ENA_DIS_DLY; i; i--);
    LCD_CTRL_bit.LcdPwr= 1;   // enable power
  }
  else
  {
    LCD_CTRL_bit.LcdPwr= 0;   // disable power
    for(volatile Int32U i = C_GLCD_PWR_ENA_DIS_DLY; i; i--);
    LCD_CTRL_bit.LcdEn = 0;
  }
}

//
// Main function: simple use (write pixel
//
int main(void){
    GLCD_Ctrl (TRUE);                                             // Enable display
    pInt32U pDst = (pInt32U) LCD_VRAM_BASE_ADDR;                  // Define and set base address
   
    for(Int32U i = 0; (C_GLCD_H_SIZE * C_GLCD_V_SIZE) > i; i++)
    {
      *pDst++ = PX_BG;                                            // Write pixel
    }
}

Michael_L

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Re: Color problem with NHD-5.0-800480TF-ATXL-CTP
« Reply #1 on: September 30, 2014, 08:09:57 AM »
To clarify, you are able to write colors blue red and green with no issues, but not combinations?  I have never heard of this issue before.  What value are you trying to write?  0x847047?  If you are trying to produce yellow, can you please try 0xFFFF00 instead?

mozart

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Re: Color problem with NHD-5.0-800480TF-ATXL-CTP
« Reply #2 on: September 30, 2014, 09:41:31 AM »
Thanks for your reply. Yes, the color I intend to use is  0x857047 but I have tried the yellow before and the result was something like pink. I'm thinking the problem may be caused by syncronization but I don't know how to verify this.

 

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