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Connecting NHD-12232AZ-FL-YBW to a Cypress PSoC 3


I am connecting a NHD-12232AZ-FL-YBW display to a Cypress PSoC 3 cpu.
The cpu has separate RD' and WR'  active-low pulses.
Your datasheet says that the connector has only one R/W instead of separate read and write lines.
The  SBN1661G_M02 datasheet says that with the RESET pulse I can switch to a 80-type interface (instead of a 68-type interface). In the 80-type interface the R/W switches to WR' and the E switches to RD'.
My question is: You have two lines E1 and E2. I assume that this is because you have two SBN1661G_M02 chips.
If so, the E1 will switch to RD'1 and E2 will switch to RD'2.
But there is a single R/W line, that will switch to WR', so how do I know if I am writing to the 1st of 2nd chip?

You are correct, there are two chips used for this display.  Each Enable signal controls one, and the R/W signal is shared (tied together) between them.  Because of this, you would not be able to use the display in 8080 mode because you would then write (with the shared /WR signal) to both chips anytime your micro sends data to the display.


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