Author Topic: NHD 5.0 800480 startup woes - SOLVED  (Read 364 times)


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NHD 5.0 800480 startup woes - SOLVED
« on: June 16, 2017, 10:25:48 AM »
I built a board with LED's for all the signals going to the display, that sits between the processor board and the NHD controller board.  Watching the display init routine run, I noticed that bits 6 & 7 were not behaving.  Turns out that those two pins had a solder bridge between them at the processor.  My display now works.

I wish to thank my parents for having me, my wife for having me, my 2 dogs and 1 cat for having me and finally myself - for without myself I would be . . . . . . not be?

Kind regards,

Seems like everytime I try a new display, I have a battle getting it to respond.  On my current project I had to switch from the 7.0 TFT to the 5.0 TFT, both 800x480 and both using the SSD1963 controller board.

Attached is a video of the display going thru the init code.  I am using Curt's eval code for the 5.0 800x480 with the SSD1963.  Oh well, the video is too big - what it shows is the display goes black, then when the init occurs, the screen turns white and you can see a horizontal line of pixels as it moved down the display.  When it reaches the bottom, the screen stays mostly white, except for the upper third has darkend - looks a lot like a thunderstorm cloud.  Ok, so I could include a reduced version photo of the screen as the line scans down the display.

I have single stepped through the TFT_5_Write_Data and the TFT_5_Write_Command functions and verified the signals to the controller board - on the controller board.

I have included the code below.

Any suggestions?
Kind regards,

void TFT_5_Write_Data (unsigned char data1)  //no joy with delays
   AVR32_GPIO.port[1].ovr = data1;

void TFT_5_Write_Command (unsigned char command)
   int x;
   AVR32_GPIO.port[1].ovr = command;

void TFT_5_WindowSet(int s_x, int e_x, int s_y, int e_y)
   int s_x_c;  //Start_X_Corrected
   s_x_c = e_x - s_x;
   TFT_5_Write_Command(0x2a);      //set page address
   TFT_5_Write_Data((s_x)>>8);      //set start page address = 0
   TFT_5_Write_Data((e_x)>>8);      //set end page address 639
   TFT_5_Write_Command(0x2b);      //set column address
   TFT_5_Write_Data((s_y)>>8);      //set start column address = 0
   TFT_5_Write_Data((e_y)>>8);      //set end column address = 459
void TFT_5_Init(void)
   //new setup as of 06-15-17
   TFT_5_Write_Command(0x01);     //Software Reset
   TFT_5_Write_Command(0x01);     //Software Reset

   TFT_5_Write_Command(0xe0);    //START PLL
   TFT_5_Write_Command(0xe0);    //LOCK PLL
   TFT_5_Write_Command(0xb0);      //SET LCD MODE (7 parameters)
   TFT_5_Write_Data(0x08);         //18-bit, TFT FRC enable, dithering off
   TFT_5_Write_Data(0x80);         //LCD panel mode
   TFT_5_Write_Data(0x03);         //SET horizontal size=800-1 HightByte
   TFT_5_Write_Data(0x1f);          //SET horizontal size=800-1 LowByte
   TFT_5_Write_Data(0x01);         //SET vertical size=480-1 HightByte
   TFT_5_Write_Data(0xdf);         //SET vertical size=480-1 LowByte
   TFT_5_Write_Data(0x00);         //SET even/odd line RGB seq.=RGB
   TFT_5_Write_Command(0xf0);      //SET pixel data I/F format=8bit
   TFT_5_Write_Command(0x36);   //SET address mode=flip vertical
   TFT_5_Write_Command(0x3a);   // SET R G B format = 6 6 6
   TFT_5_Write_Command(0xe2);         //SET PCLK freq=9.5MHz  ; pixel clock frequency
   TFT_5_Write_Command(0xe6);         //SET PCLK freq=9.5MHz  ; pixel clock frequency
   TFT_5_Write_Command(0xb4);      //SET Horizontal Period (8 parameters)
   TFT_5_Write_Data(0x04);         //SET HSYNC Total=1056
   TFT_5_Write_Data(0x00);         //SET HSYNC Start Position=88
   TFT_5_Write_Data(0x80);         //SET HSYNC Pulse Width=128=127pixels+1
   TFT_5_Write_Data(0x00);         //SET HSYNC pulse start position=0
   TFT_5_Write_Data(0x00);         //SET HSYNC pulse subpixel start position
   TFT_5_Write_Command(0xb6);       //SET Vertical Period (7 parameters),
   TFT_5_Write_Data(0x02);         //SET Vsync total=525
   TFT_5_Write_Data(0x00);         //SET VSYNC Pulse Start Position=32
   TFT_5_Write_Data(0x01);         //SET VSYNC Pulse Width= 0=0lines+1
   TFT_5_Write_Data(0x00);         //SET VSYNC Pulse Start Position=0
   TFT_5_Write_Command(0x2a);      //SET column address
   TFT_5_Write_Data(0x00);         //SET start column address=0
   TFT_5_Write_Data(0x03);         //SET end column address=799
   TFT_5_Write_Command(0x2b);      //SET page address
   TFT_5_Write_Data(0x00);         //SET start page address=0
   TFT_5_Write_Data(0x01);         //SET end page address=479
   TFT_5_Write_Command(0x13);      //SET normal mode
   TFT_5_Write_Command(0x38);      //SET normal mode
   TFT_5_Write_Command(0x29);      //SET display on
« Last Edit: June 24, 2017, 08:59:48 PM by dfansler »


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