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1
OLEDs / Re: NHD Slim OLED Character Display Driver for STM32
« Last post by Florence5 on June 19, 2019, 11:48:24 PM »
Yes actually it is very useful for users like us..Thanks a lot for sharing..Keep us updated though school bucks
2
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« Last post by mike_s on June 19, 2019, 06:46:34 PM »
Hi Mike_S,

It's good to hear you have it working!

You are correct that the 7.0" TFT is setup to work in DE mode by default.  The display's Data Enable mode is Active High at pin 34 to enable the data input bus.

Best Regards,

Hi Ted,


If you all are certain that the pin34 DE is definitely ACTIVE HIGH logic, then that means STMicro messed up their data sheet, since I had to set the LTDC -> DE polarity to 'Active Lo'....

but of course their wording could also be a 'double negative', when they say 'not data enable polarity is active low'... which would mean Active Hi. LOL

anyhow, this is good info for anyone that ends up using an STM32xxx processor with the LTDC controller, so they know the datasheet is backwards...
3
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« Last post by Ted_M on June 19, 2019, 04:53:59 PM »
Hi Mike_S,

It's good to hear you have it working!

You are correct that the 7.0" TFT is setup to work in DE mode by default.  The display's Data Enable mode is Active High at pin 34 to enable the data input bus.

Best Regards,
4
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« Last post by mike_s on June 19, 2019, 03:27:58 PM »
Ok,

I got it all working... the DE POLARITY was backwards, at least according to the STM32H7 datasheet, so I don't know whom is right, the NewHaven TFT datasheet, or the STM32H7 datasheet.

But in order for DE to work, I had to set:

** From the STM32H7 datasheet **


Code: [Select]
DEPOL: not data enable polarity
This bit is set and cleared by software.
0: not data enable polarity is active low.   <<<==== had to set to ACTIVE LOW
1: not data enable polarity is active high.

with it ACTIVE HIGH there is NO display.... only thing I could do to prove it out would be to scope it up, but right now I just want to install the screen and get it working.

(I also verified I could disable DE altogether by installing that R4 short, which I did to verify the screen worked, then removed it, as I want to use the default of 'DE' being enabled.


So for now the screen works!  But I'm concerned as to which vendor is right... is the STMicro datasheet backwards, or is the datasheet wrong for the LCD, and 'DE' is actually ACTIVE LOW, not high?

5
TFTs / Re: NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« Last post by mike_s on June 19, 2019, 10:42:17 AM »
Actually,

I think I see something, I'll be trying this today when I get home from work...

1) PCLK needs to be inverted for this LCD

2) ** most ** important, sounds like this 7.0" TFT is setup by default to use 'DE' mode, whereas the 5.0" probably was not?

(my LTDC controller does have the DE pin, but by default it was setup as 'active LOW', and I have the pin pulled down), so it sounds like the 5.0" was probably not using it which is why my setup still worked, but the 7.0" I need to switch the pin polarity)


Ie I see a discussion just like this in a old thread from 2014..

https://www.newhavendisplay.com/NHD_forum/index.php/topic,67.15.html


I'll report back after testing this evening :)



6
TFTs / Re: ISSUE WHILE READING CHIPID IN DISPLAY (FT813)
« Last post by Ted_M on June 19, 2019, 08:37:43 AM »
Hi Arjun,

Try reducing the SPI clock to less than 11Mhz before sending the Active command.
Please see Page 11 of the FT81X Series Programmers Guide for reading the chip identification code and the recommended initialization when booting up the display:

https://brtchip.com/wp-content/uploads/Support/Documentation/Programming_Guides/ICs/EVE/FT81X_Series_Programmer_Guide.pdf

Send Host command “ACTIVE” to enable the clock to the FT81X.
FT81X starts its self diagnosis process and may take up to 300ms.
Alternatively, read REG_ID repeatedly until 0x7C is read.

After reset or reboot, the chip ID can be read from address 0xC0000 to 0xC0003.

Best Regards,
7
TFTs / Re: ISSUE WHILE READING CHIPID IN DISPLAY (FT813)
« Last post by Arjun on June 19, 2019, 06:04:07 AM »
Hello,

Thank you for your response Sir. Now we are able to read 5mA in SCLK pin but still not able to read chip id.

Description:

Able to send commands to LCD Driver (FT813), the response for chip id always 0(zero).

What could be the reason? Is that we are missing something in code?

Commands Sent to FT813 from ATMEGA2560:

Code Flow:

1) Port and SPI Initialization
2) Power-down command
3) External clock command
4) Active command
5) Read REG ID(0x302000)

When Power down command is sent to FT813, display will get enabled(ON) and for Active command it goes to disable(OFF) state. Is this code execution is correct or anything need to be included.
8
TFTs / NHD-5.0-800480TF-ATXL#-CTP VS. NHD-7.0-800480EF-ASXN#-CTP
« Last post by mike_s on June 19, 2019, 05:54:59 AM »
Hi All,

I have a current project using an STM32H7 micro, which has a built-in LTDC display controller.  I have it working fine with the 5.0" display as mentioned in the topic.

I wanted to then see how much better it would be with the 7.0" display, which appears to be an identical electrical interface, with the exception of the LCD Backlight voltage being 9.6V on the 7.0" versus 19.2V on the 5.0".

I realize the controller chips changed:

1) 5.0" ==  ILI6126C
2) 7.0" == HX8264-D02


I tried the 7.0" display on both of my boards (which both work fine with 5.0" displays), and I get absolutely nothing on the screens except for the initial white backlight when it first boots up...

I've played with the timings, I/O drive strength, pixel clock, etc, with zero effect. 

I did notice that the PCLK on the 5.0" says it's rising edge triggered, versus the 7.0" which is falling edge triggered.. but I haven't tried inverting the PCLK polarity yet, do I need to make that change for the 7.0" TFT?

Is anyone aware of anything else that may need to be changed when going from the ILI6126C controller to the HX8264??


(I've opened an RMA request suspecting that the display may be bad, but I realize they do test these screens before they are shipped out, so I wonder if there is still something I'm missing???)


Thanks so much,

- Mike
9
TFTs / NHD-4.3-480272EF-ASXN# Backlight but no Graphic Data
« Last post by danr on June 19, 2019, 12:40:00 AM »
Hi,

We are using the NHD-4.3-480272EF-ASXN# in a product that we expect to deliver soon.
However, we are currently blocked since we haven't been able to solve an issue with the LCD.
Can you please help us fix this?


The issue is that on a cold start (and sometimes almost cold - 100mV to 300mV), the LCD sometimes enters a state where the backlight can be active, but there is no graphic data.
All of the RGB bits are present, PCLK is active, and so are HSYNC and DEN.
VSYNC is held low.

When the LCD is in either a working or a failed state, quick power cycles do not cause a change.
it is only when we let VDD to drain to 0V (cold start) that there isd a chance of the LCD changing from a healthy state to a faulty state, or vice versa.


We have the NHD-4.3-480272EF-ASXN# connected to a BeagleBone Black Industrial, and have tried different timing parameters.




At first, by accident we had the wrong parameters which carried over from a completely different LCD.
These parameters cause the LCD to enter either of the aforementioned states.

Code: [Select]
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <47>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <3>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;




After we noticed this, we corrected the timing parameters to match the NHD-4.3-480272EF-ASXN# datasheet.
In this state the LCD seemed to appear as though it was always working.
However, the chip that delivers the RGB data, PCLK and sync signals to the LCD automatically filters any HSYNC or VSYNC pulses that are less than 2 full PCLK cycles.
When I disable this filtering to allow HSYNC through, the graphic data slowly fades away, leaving only the backlight.
This led us to believe that the issue is due to timing, and that we were getting closer.
Have a look at this video:
https://rctglobal-my.sharepoint.com/:v:/g/personal/danr_rct-global_com/EWR9me0_vXZPpMP6sw-vQkEBlXDMFyJYGIxhXaVP2iLAqQ?e=P6O0gj

Code: [Select]
clock-frequency = <12000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <2>;
hback-porch = <43>;
hsync-len = <1>;
vback-porch = <12>;
vfront-porch = <1>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;




We are worried because we can't see VSYNC being generated by the BeagleBone under these settings and that the screen fades away when we let HSYNC through.

The screen seems to work correctly, until we allow HSYNC through.
Are we worrying about nothing here, the filtering is working in our favour?
Will we face problems without VSYNC and from removing HSYNC?
(DEN is active in all of the above scenarios).


We also noticed that the timing in the NHD-4.3-480272EF-ASXN# is completely different to the timing in the ST7282T2 datasheet.
See attached.
Which one is correct?

The typical settings from the ST7282T2 datasheet cause the screen to immediately turn white, just like the first set of settings that we had. This led us to believe that the settings in the NHD-4.3-480272EF-ASXN# is more correct but we are unsure if there is something else causing this.


Kind regards,
Dan

10
TFTs / Re: ISSUE WHILE READING CHIPID IN DISPLAY (FT813)
« Last post by Ted_M on June 18, 2019, 11:18:38 AM »
Hi Arjun,

Please try 5mA on the SCLK. A hardware buffer to provide the extra current has also worked for other users with similar issues.

Best Regards,
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