Newhaven Display Forum

OK, if I understand you correctly you want the LCD to 'snoop' on the serial stream and be completely agnostic to the sync protocol. Presumably this means the packets that you send contain a start address for each packet (the first character position for that chunk of data) which you would need in order for the display not to increment its address counter past the displayable area. If that's the case changing the address to somewhere in the non-displayable area should work, and that address could be the flag that it's a sync packet that indicates that the switch has to send a response back to the host. Is that correct?
Mark.

According to the ST7032 spec the SDA and SCL lines are on DB7 and DB6 respectively. These have a Vol spec of 0.8V with Iol of 1mA (quoted at 25deg C), so that's an equivalent resistance of 3k3 at 3.3V. Generally I2C works well with 4k7 to 10k, so I'd probably use 10k here for some margin, in theory that should get down to less than 0.4V. A 1k5 ohm resistance is too low to get a low enough Vol.

Mark.

Edit: OK, I see a problem. You're final SCL clock looks way too short, is this a software I2C master interface you're using? Can you change the pull-up resistors to 10k, and give a proper length SCL pulse at the end? Sampling closer to the rising edge of SCL might help, it shouldn't be changing the SDA state while the clock is high though.

Edit2: There are small spikes on the SDA at the point where SCL changes. As SDA is open colector and pulled up by a resistor that suggests some noice on Vcc. If the device has feedback internally on SDA, and a too low value of resistor is used meaning the logic low is a little close to the edge, and there's Vcc noise, it's possible that the logic inside the controller lets go of SDA prematurely. So by putting a high value of resistor in you've pulled the signal down, meaning it can tolerate more Vcc noise. At the 50k limit it appears to work, Vcc noise is not enough to trigger a release. I would look carefully then at Vcc, put some decoupling caps close to the module and try to get rid of those little spikes. A combination of using 10k resistors and decent Vcc decoupling may be the solution.

Thanks, but I'm a little confused as there is a base-emitter diode drop between VO and VEE of the PNP transistor (about 0.65V) in the temperature compensation circuits. Also VDD-VO is specified as 3.3V typical (no minimum or maximum given), presumably typical is at typical temperature and VDD voltage, so VO would be typically 0V and we need at least -0.65V for VEE just for that case. Lowering the temperature to -20degC is going to require a more negative voltage than 0V on VO so this requires even more negative voltage on VEE. Or have I misunderstood something?

Mark.

Hi,
I'm trying to design a temperature compensation circuit for the 3.3V NHD-0108CZ-FSW-GBW-33V3 module to be used in a commercial product. This is a 'wide' temperature range module, so I presume I have to generate a negative VEE voltage and use your app note using an NTC resistor and PNP transistor in order to temperature compensate across the full range (-20 to +70 deg C).

What would be a good VEE voltage to use for this? Do you have any recommended compensation circuits for this 3.3V module? Your application notes all appear to be for 5V modules, and this module has a VO pin instead of VL, so I'm unsure exactly how to proceed.

Thanks,
Mark.