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« on: April 30, 2016, 06:13:19 PM »
According to the ST7032 spec the SDA and SCL lines are on DB7 and DB6 respectively. These have a Vol spec of 0.8V with Iol of 1mA (quoted at 25deg C), so that's an equivalent resistance of 3k3 at 3.3V. Generally I2C works well with 4k7 to 10k, so I'd probably use 10k here for some margin, in theory that should get down to less than 0.4V. A 1k5 ohm resistance is too low to get a low enough Vol.
Mark.
Edit: OK, I see a problem. You're final SCL clock looks way too short, is this a software I2C master interface you're using? Can you change the pull-up resistors to 10k, and give a proper length SCL pulse at the end? Sampling closer to the rising edge of SCL might help, it shouldn't be changing the SDA state while the clock is high though.
Edit2: There are small spikes on the SDA at the point where SCL changes. As SDA is open colector and pulled up by a resistor that suggests some noice on Vcc. If the device has feedback internally on SDA, and a too low value of resistor is used meaning the logic low is a little close to the edge, and there's Vcc noise, it's possible that the logic inside the controller lets go of SDA prematurely. So by putting a high value of resistor in you've pulled the signal down, meaning it can tolerate more Vcc noise. At the 50k limit it appears to work, Vcc noise is not enough to trigger a release. I would look carefully then at Vcc, put some decoupling caps close to the module and try to get rid of those little spikes. A combination of using 10k resistors and decent Vcc decoupling may be the solution.